Cheatsheets

VHDL

Entities, architectures, types, concurrent & sequential (process) statements.

Visualize

Digital logic — a clocked timing diagram

Synchronous logic only changes on the rising clock edge; reset forces a known state.

clkrstq[2:0]

Press play — the cursor sweeps time; q steps on each rising clk edge.

21 entries

Entity & architecture5

entity counter is
  port (
    clk : in  std_logic;
    q   : out std_logic_vector(7 downto 0)
  );
end entity;

Complete 8-bit counter with synchronous reset.

architecture rtl of counter is
begin
  -- logic here
end architecture;

Architecture = the implementation

in / out / inout / buffer

Port directions

signal s : std_logic;

Internal wire (declared in architecture)

u1 : entity work.foo port map (a => x, b => y);

Instantiate a component

Data types6

std_logic / std_logic_vector(7 downto 0)

Single bit / bus (ieee.std_logic_1164)

'0' '1' 'Z' 'X' '-'

Logic levels (low, high, hi-Z, unknown, don't-care)

unsigned / signed

Arithmetic vectors (ieee.numeric_std) — convert to/from std_logic_vector.

x"FF" b"1010"

Hex / binary literals

integer range 0 to 255

Constrained integer

type state_t is (IDLE, RUN, DONE);

Enumerated type (for FSMs)

Concurrent statements4

q <= a and b;

Concurrent signal assignment

y <= a when sel = '1' else b;

Conditional assignment

with sel select y <= a when "00", b when others;

Selected assignment

<= after 5 ns

Inertial delay — simulation only, NOT synthesizable.

Sequential (process)5

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

Clocked (synchronous) register.

if / elsif / else ... end if;

Sequential branch

case sel is when "00" => ...; when others => ...; end case;

Sequential case

variable v : integer := 0;

Process variable (`:=` assigns immediately)

rising_edge(clk) / falling_edge(clk)

Clock edge detection

Simulation & testbench1

Testbench

Recipe: verify a module by driving a clock and checking outputs.