Cheatsheets

Verilog

Modules, wire/reg, blocking vs non-blocking, and always blocks.

Visualize

Synchronous logic only changes on the rising clock edge; reset forces a known state.

clkrstq[2:0]

Press play — the cursor sweeps time; q steps on each rising clk edge.

18 entries

module counter (
  input            clk,
  input            rst_n,
  output reg [7:0] q
);
endmodule

Complete 8-bit counter with synchronous reset.

input / output / inout

Port directions

foo u1 (.a(x), .b(y));

Instantiate by name

parameter WIDTH = 8;

Compile-time parameter

`define MAX 255

Preprocessor macro

wire

Continuous connection (driven by assign / output)

reg

Holds a value (assigned in always/initial)

[7:0] bus

8-bit vector — mind the width on arithmetic.

8'hFF 4'b1010 8'd255

Sized hex / binary / decimal literals

logic (SystemVerilog)

Unified type replacing wire/reg

assign y = a & b;

Continuous (combinational) assignment

<= (non-blocking) vs = (blocking)

The #1 Verilog gotcha — pick by block type.

y = sel ? a : b;

Ternary mux

always @(posedge clk) begin
  if (rst) q <= 0;
  else     q <= q + 1;
end

Synchronous (sequential) logic — non-blocking.

always @(*) begin
  case (sel)
    2'b00: y = a;
    default: y = b;
  endcase
end

Combinational logic — blocking, full case.

always @(posedge clk or negedge rst_n)

Async reset sensitivity

Testbench

Recipe: drive a clock and observe with $monitor.

initial begin ... end

Runs once at t=0 (testbench)